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74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
May 1991 Revised May 2005
74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ACTQ16244 utilizes Fairchild's Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance.
Features
s Utilizes Fairchild's FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte and nibble s 16-bit version of the ACTQ244 s Outputs source/sink 24 mA s Additional specs for multiple output switching s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number 74ACTQ16244SSC 74ACTQ16244MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Description
Pin Names OEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Inputs Outputs
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS010925
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74ACTQ16244
Connection Diagram
Functional Description
The ACTQ16244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The 3STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H Inputs I4-I7 L H X I0-I3 L H X Outputs O0-O3 L H Z Outputs O4-O7 L H Z Outputs I8-I11 L H X Inputs OE4 L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
Logic Diagram
OE3 L L H
O8-O11 L H Z Outputs
I12-I15 L H X
O12-O15 L H Z
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74ACTQ16244
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI VO
0.5V to 7.0V 20 mA 20 mA
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
4.5V to 5.5V 0V to VCC 0V to VCC
0.5V VCC 0.5V 0.5V VCC 0.5V
DC Output Diode Current (IOK)
20 mA 20 mA VO 0.5V to VCC 0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) r50 mA
DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature
40qC to 85qC
125 mV/ns
r50 mA 140qC 65qC to 150qC
DC Electrical Characteristics
Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC Droop Minimum HIGH Dynamic Input Voltage Level Maximum LOW Dynamic Input Voltage Level 5.0 5.0 5.0 5.0 5.0 5.0 0.5 0.8 5.5 5.5 5.5 5.5 0.6 8.0 5.5 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36
25qC
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Units VOUT VOUT
Conditions 0.1V 0.1V
Guaranteed Limits V V V or VCC 0.1V or VCC 0.1V IOUT VIN V IOH IOH V IOUT VIN V IOH IOH VI VO VI VI VIN VOLD VOHD
50 PA
VIL or VIH
24 mA 24 mA (Note 2)
50 PA VIL or VIH 24 mA 24 mA (Note 2) VIL, VIH VCC, GND VCC, GND VCC 2.1V VCC or GND (Note 6) 1.65V Max 3.85V Min
r 0.5 r 0.1
r 5.0 r 1.0
1.5 80.0 75
PA PA
mA
PA
mA mA V V V V V V
75
Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) (Note 4)(Note 6) (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7)
0.5
1.0
VOH 1.0 VOH 1.5 VOH 1.0 VOH 1.8 1.7 1.2 2.0 0.8
Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. Note 4: Worst case package. Note 5: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched LOW and one output held LOW. Note 6: Maximum number of outputs that can switch simultaneously is n. (n 1) outputs are switched HIGH and one output held HIGH. Note 7: Max number of data inputs (n) switching. (n 1) input switching 0V to 3V input under test switching 3V to threshold (VILD)
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74ACTQ16244
AC Electrical Characteristics
VCC Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay An, Bn to Bn, An Output Enable Time Output Disable Time 5.0 5.0 5.0 Parameter (V) (Note 8) Min 3.0 2.5 2.5 2.7 2.3 2.0 TA CL
25qC
50 pF Typ 5.2 4.8 5.0 4.6 5.0 4.6 Max 7.3 6.8 7.4 7.5 7.9 7.4
TA
40qC to 85qC
CL 50 pF Max 7.8 7.3 7.9 8.0 8.2 7.9 ns ns ns Units
Min 3.0 2.5 2.5 2.7 2.3 2.0
Note 8: Voltage Range 5.0 is 5.0V r 0.5V.
Extended AC Electrical Characteristics
TA
40qC to 85qC
CL 50 pF TA
40qC to 85qC
CL 250 pF Units (Note 12)
Symbol
Parameter
VCC (V) (Note 8)
16 Outputs Switching (Note 11) Min 4.0 3.4 3.5 3.4 3.6 3.1 Typ Max 11.6 9.6 10.1 10.0 8.9 8.1 1.2 2.5 4.3
Min 5.6 4.8
Max 14.3 13.1 ns ns ns ns ns ns
tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 10) tOSLH (Note 10) tOST (Note 10)
Propagation Delay Data to Output Output Enable Time Output Disable Time Pin to Pin Skew HL Data to Output Pin to Pin Skew LH Data to Output Pin to Pin Skew LH/HL Data to Output
5.0 5.0 5.0 5.0 5.0 5.0
(Note 13) (Note 14)
Note 9: Voltage Range 5.0 is 5.0V r 0.5V. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 14: The Output Disable Time is dominated by the RC network (500:, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol CIN CPD Input Pin Capacitance Power Dissipation Capacitance Parameter Typ 4.5 30 Units pF pF VCC VCC 5.0V 5.0V Conditions
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74ACTQ16244
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500:. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and affect the results of the measurement. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements
3 ns,
VOHV and VOLP are measured with respect to ground reference. Input pulses have the following characteristics: f tf 3 ns, skew 150 ps. 1 MHz, tr
FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ16244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74ACTQ16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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